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72-mbit qdr?-ii+ sram 4-word burst architecture (2.0 cycle read latency) cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-05389 rev. *f revised march 06, 2008 features separate independent read and write data ports ? supports concurrent transactions 375 mhz clock for high bandwidth 4-word burst for reducing address bus frequency double data rate (ddr) interfaces on both read and write ports (data transferred at 750 mhz) at 375 mhz available in 2.0 clock cycle latency two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high-speed systems data valid pin (qvld) to indicate valid data on the output single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes available in x8, x9, x18, and x36 configurations full data coherency, providing most current data core v dd = 1.8v 0.1v; io v ddq = 1.4v to v dd [1] hstl inputs and variable drive hstl output buffers available in 165-ball fbga package (15 x 17 x 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1 compatib le test access port delay lock loop (dll) for accurate data placement configurations with read cycle latency of 2.0 cycles: cy7c1541v18 ? 8m x 8 cy7c1556v18 ? 8m x 9 cy7c1543v18 ? 4m x 18 cy7c1545v18 ? 2m x 36 functional description the cy7c1541v18, cy7c1556v18, cy7c1543v18, and cy7c1545v18 are 1.8v synchronous pipelined srams, equipped with qdr-ii+ architectu re. similar to qdr-ii archi- tecture, qdr-ii+ srams consists of two separate ports: the read port and the write port to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data input s to support write operations. qdr-ii+ architecture has separa te data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus that exists with common io dev ices. each port is accessed through a common address bus. addresses for read and write addresses are latched on alternate rising edges of the input (k) clock. accesses to the qdr-ii+ read and write ports are completely independent of one another. to maximize data throughput, both read and write ports are equipped with ddr interfaces. each address location is associated with four 8-bit words (cy7c1541v18), 9-bit words (cy7c1556v18), 18-bit words (cy7c1543v18), or 36-bit words (cy7c1545v18) that burst sequentially into or out of the device. because data is trans- ferred into and out of the devic e on every rising edge of both input clocks (k and k ), memory bandwidth is maximized while simpli- fying system design by elimi nating bus ?turn-arounds?. depth expansion is accomplished with port selects, which enables each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the k or k input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide description 375 mhz 333 mhz 300 mhz unit maximum operating frequency 375 333 300 mhz maximum operating current x8 1300 1200 1100 ma x9 1300 1200 1100 x18 1300 1200 1100 x36 1370 1230 1140 note 1. the qdr consortium specification for v ddq is 1.5v + 0.1v. the cypress qdr dev ices exceed the qdr consor tium specification and are capable of supporting v ddq = 1.4v to v dd . [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 2 of 28 logic block diagram (cy7c1541v18) logic block diagram (cy7c1556v18) 2m x 8 array clk a (20:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 16 21 32 8 nws [1:0] v ref write add. decode write reg 16 a (20:0) 21 2m x 8 array 2m x 8 array 2m x 8 array 8 cq cq doff q [7:0] 8 qvld 8 8 8 write reg write reg write reg 2m x 9 array clk a (20:0) gen. k k control logic address register d [8:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 18 21 36 9 bws [0] v ref write add. decode write reg 18 a (20:0) 21 2m x 9 array 2m x 9 array 2m x 9 array 9 cq cq doff q [8:0] 9 qvld 9 9 9 write reg write reg write reg [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 3 of 28 logic block diagram (cy7c1543v18) logic block diagram (cy7c1545v18) 1m x 18 array clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 36 20 72 18 bws [1:0] v ref write add. decode write reg 36 a (19:0) 20 1m x 18 array 1m x 18 array 1m x 18 array 18 cq cq doff q [17:0] 18 qvld 18 18 18 write reg write reg write reg 512k x 36 array clk a (18:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 72 19 144 36 bws [3:0] v ref write add. decode write reg 72 a (18:0) 19 512k x 36 array 512k x 36 array 512k x 36 array 36 cq cq doff q [35:0] 36 qvld 36 36 36 write reg write reg write reg [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 4 of 28 pin configuration the pin configuration for cy7c1541v18, cy7c1556 v18, cy7c1543v18, and cy7c1545v18 follow. [2] 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1541v18 (8m x 8) 1 2 3 4 5 6 7 8 9 10 11 a cq aawps nws 1 k nc/144m rps aacq b nc nc nc a nc/288m k nws 0 ancncq3 c nc nc nc v ss ancav ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss aaav ss nc nc nc p nc nc q7 a a qvld a a nc nc nc r tdotckaaancaaatmstdi cy7c1556v18 (8m x 9) 1 2 3 4 5 6 7 8 9 10 11 a cq aawps nc k nc/144m rps aacq b nc nc nc a nc/288m k bws 0 ancncq4 c nc nc nc v ss ancav ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss aaav ss nc nc nc p nc nc q8 a a qvld a a nc d0 q0 r tdotckaaancaaatmstdi note 2. nc/144m and nc/288m are not connected to the die and can be tied to any voltage level. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 5 of 28 cy7c1543v18 (4m x 18) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/144m a wps bws 1 k nc/288m rps aacq b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 v ss ancav ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss aaav ss nc nc d1 p nc nc q17 a a qvld a a nc d0 q0 r tdotckaaancaaatmstdi cy7c1545v18 (4m x 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/288m a wps bws 2 k bws 1 rps a nc/144m cq b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss ancav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a qvld a a q9 d0 q0 r tdotckaaancaaatmstdi pin configuration (continued) the pin configuration for cy7c1541v18, cy7c1556 v18, cy7c1543v18, and cy7c1545v18 follow. [2] 165-ball fbga (15 x 17 x 1.4 mm) pinout [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 6 of 28 pin definitions pin name io pin description d [x:0] input- synchronous data input signals. sampled on the rising edge of k and k clocks when valid write operations are active . cy7c1541v18 ? d [7:0] cy7c1556v18 ? d [8:0] cy7c1543v18 ? d [17:0] cy7c1545v18 ? d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. dea sserting deselects the write port. de selecting the write port ignores d [x:0] . nws 0 , nws 1 , input- synchronous nibble write select 0, 1 ? active low (cy7c1541v18 only) . sampled on the rising edge of the k and k clocks when write operations are active. used to se lect which nibble is written into the device during the current portion of the write operations. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the same edge as the data. deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low . sampled on the rising edge of the k and k clocks when write operations are active. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1556v18 ? bws 0 controls d [8:0] cy7c1543v18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1545v18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select ignores the corresponding byte of data and it is not written into the device . a input- synchronous address inputs . sampled on the rising edge of the k clock du ring active read and write operations. these address inputs are multiplexed for both read and writ e operations. internally, the device is organized as 8m x 8 (4 arrays each of 2m x 8) for cy7c1541v18, 8m x 9 (4 arrays each of 2m x 9) for cy7c1556v18, 4m x 18 (4 arrays each of 1m x 18) for cy7c1543v18 and 2m x 36 (4 arrays each of 512k x 36) for cy7c1545v18. therefore, only 21 address inputs ar e needed to access the entire memory array of cy7c1541v18 and cy7c1556v18, 20 address inputs for cy7c1543v18 and 19 address inputs for cy7c1545v18. these inputs are ignored when the appropriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data when the read operation is active. valid data is driven out on the rising edge of the k and k clocks during read operati ons. on deselecting the read port, q [x:0] are automatically tri-stated. cy7c1541v18 ? q [7:0] cy7c1556v18 ? q [8:0] cy7c1543v18 ? q [17:0] cy7c1545v18 ? q [35:0] rps input- synchronous read port select ? active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasse rting deselects the read port. when deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the k clock. each read access consists of a burst of four sequential transfers. qvld valid output indicator valid output indicator . the q valid indicates valid output data. qvld is edge aligned with cq and cq . k input- clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] . all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] . cq echo clock synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k) of the qdr-ii+. the timings for the echo clocks are shown in the switching characteristics on page 23. cq echo clock synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k ) of the qdr-ii+. the timings for the echo clocks are shown in the switching characteristics on page 23. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 7 of 28 zq input output impedance matching input . this input is used to tune the dev ice outputs to the system data bus impedance. cq, cq and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off ? active low . connecting this pin to ground turns off the dll inside the device.the timings in the dll turned off operation are different from those listed in this data sheet. for normal operation, this pin can be connected to a pull up through a 10 k or less pull up resistor. the device behaves in qdr-i mode when the dll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz with qdr-i timing. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die. can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name io pin description [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 8 of 28 functional overview the cy7c1541v18, cy7c1556v18, cy7c1543v18, and cy7c1545v18 are synchronous pipelined burst srams equipped with a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs to minimize the number of address pins required. by having separate read and write ports, the qdr-ii+ completely eliminates the need to ?turn-aro und? the data bus and avoids any possible data contention, ther eby simplifyi ng system design. each access consists of four 8- bit data transfers in the case of cy7c1541v18, four 9-bit data transfers in the case of cy7c1556v18, four 18-bit data transfers in the case of cy7c1543v18, and four 36-bit data transfers in the case of cy7c1545v18, in two clock cycles. accesses for both ports are initiated on the positive input clock (k). all synchronous input and ou tput timing are referenced from the rising edge of the input clocks (k and k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) outputs pass through output registers controlled by the rising edge of th e input clocks (k and k ) as well. all synchronous control (rps , wps , nws [x:0] , bws [x:0] ) inputs pass through input registers contro lled by the rising edge of the input clocks (k and k ). cy7c1543v18 is described in the following sections. the same basic descriptions apply to cy7c1541v18, cy7c1556v18, and cy7c1545v18. read operations the cy7c1543v18 is organized internally as four arrays of 1m x 18. accesses are completed in a burst of four sequential 18-bit data words. read operations are initiated by asserting rps active at the rising edge of th e positive input clock (k). the address presented to address inputs are stored in the read address register. following the next two k clock rise, the corre- sponding lowest order 18-bit word of data is driven onto the q [17:0] using k as the output timi ng reference. on the subse- quent rising edge of k , the next 18-bit data word is driven onto the q [17:0] . this process continues until all four 18-bit data words have been driven out onto q [17:0] . the requested data is valid 0.45 ns from the rising edge of the input clock (k or k ). to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and takes two clock cycles to complete. t herefore, read accesses to the device cannot be initiated on two consecutive k clock rises. the internal logic of the device ignores the second read request. read accesses can be initiated on every other k clock rise. doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (k and k ). when the read port is dese lected, the cy7c1543v18 first completes the pending read transactions. synchronous internal circuitry automatically tri-stat es the outputs following the next rising edge of the positive input clock (k). this enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are init iated by asserting wps active at the rising edge of the positive input cock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subseque nt rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. this process continues fo r one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the memory array at the specified location. therefore, write a ccesses to the device cannot be initiated on two consecutive k clock rises. the internal logic of the device ignores the second write request. write accesses can be initiated on every other rising edge of the positive input clock (k). doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when deselected, the write port ignores all inputs after the pending write operations have been completed. byte write operations byte write operations are su pported by the cy7c1543v18. a write operation is initiated as described in the write operations section. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte wr ite select input during the data portion of a write latches the da ta being presented and writes it into the device. deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read, modify, or writ e operations to a byte write operation. concurrent transactions the read and write ports on the cy7c1543v18 operate completely independently of one another. as each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. if the ports access the same location when a read follows a write in successive clock cycles , the sram delivers the most recent information associated with the specified address location. this inclu des forwarding data from a write cycle that was initiated on the previous k clock rise. read access and write access must be scheduled such that one transaction is initiated on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on the previous state of the sram. if both ports are deselected, the read port takes priority. if a read was initiated on the previous cycle, the write port assumes priority (as read operations cannot be initiated on consecutive cycles). if a write was initiated on the previous cycle, the read port as sumes priority (as write opera- tions cannot be initiated on co nsecutive cycles ). therefore, asserting both port selects active from a deselected state results in alternating read or write operati ons being initiated, with the first access being a read. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 9 of 28 depth expansion the cy7c1543v18 has a port select input for each port. this enables for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the s pecified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed before the device is deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impe dance matching with a tolerance of 15% is between 175 and 350 , with v ddq =1.5v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in su pply voltage and temperature. echo clocks echo clocks are provided on the q dr-ii+ to simplify data capture on high-speed systems. two echo clocks ar e generated by the qdr-ii+. cq is referenced with respect to k and cq is refer- enced with respect to k . these are free-running clocks and are synchronized to the input clock of the qdr-ii+. the timing for the echo clocks is shown in switching characteristics on page 23. valid data indicator (qvld) qvld is provided on the qdr-ii+ to simplify data capture on high speed systems. the qvld is ge nerated by the qdr-ii+ device along with data output. this signal is also edge-aligned with the echo clock and follows the timing of any data pin. this signal is asserted half a cycle befo re valid data arrives. dll these chips use a delay lock loop (dll) that is designed to function between 120 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. when the dll is tu rned off, the device behaves in qdr-i mode (with 1.0 cycle latency and a longer access time). for more information, refer to the application note, ?dll consid- erations in qdrii/ddrii/qdrii+ /ddrii+?. the dll can also be reset by slowing or stoppi ng the input clocks k and k for a minimum of 30ns. however, it is not necessary to reset the dll to lock to the desired frequency. during power up, when the doff is tied high, the dll is lo cked after 2048 cycles of stable clock. application example figure 1 shows four qdr-ii+ used in an application. figure 1. application example bus master (cpu or asic) data in data out address source k source k vt vt vt r r clkin/clkin d a k sram #4 rq = 250 ohms zq cq/cq q k rps wps bws d a k sram #1 rq = 250 ohms zq cq/cq q k rps wps bws rps wps bws r = 50ohms, vt = v /2 ddq r [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 10 of 28 the truth table for cy7c1541v18, cy7c1556v 18, cy7c1543v18, and cy7c1545v18 follows. [3, 4, 5, 6, 7, 8] truth table operation k rps wps dq dq dq dq write cycle: load address on the rising edge of k; input write data on two consecutive k and k rising edges. l-h h [9] l [10] d(a) at k(t + 1) d(a + 1) at k (t +1) d(a + 2) at k(t + 2) d(a + 3) at k (t + 2) read cycle: (2.0 cycle latency) load address on the rising edge of k; wait two cycles; read data on two consec- utive k and k rising edges. l-h l [10] x q(a) at k(t + 2) q(a + 1) at k (t + 2) q(a + 2) at k(t + 3) q(a + 3) at k (t + 3) nop: no operation l-h h h d = x q = high-z d = x q = high-z d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state previous state previous state the write cycle description table for cy7c1541v18 and cy 7c1543v18 follows. [3, 11] write cycle descriptions bws 0 / nws 0 bws 1 / nws 1 k k comments l l l?h ? during the data portion of a write sequence : cy7c1541v18 ? both nibbles (d [7:0] ) are written into the device, cy7c1543v18 ? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence : cy7c1541v18 ? both nibbles (d [7:0] ) are written into the device, cy7c1543v18 ? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence : cy7c1541v18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1543v18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence : cy7c1541v18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1543v18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence : cy7c1541v18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1543v18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence : cy7c1541v18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1543v18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 3. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 4. device powers up deselected with the outputs in a tri-state condition. 5. ?a? represents address location latched by the devices when trans action was initiated. a + 1, a + 2, and a + 3 represents the address sequence in the burst. 6. ?t? represents the cycle at which a read/wr ite operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ?t? clock cycle. 7. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges, also. 8. it is recommended that k = k = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging s ymmetrically. 9. if this signal was low to initiate the previous cycl e, this signal becomes a ?don?t care? for this operation. 10. this signal was high on previous k clock rise. initiating c onsecutive read or write operations on consecutive k clock rises is not permitted. the device ignores the second read or write request. 11. is based on a write cycle was initiated per the the write cycle description table for cy7c1541v18 and cy7c1543v18 follows. [3, 11] table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 11 of 28 the write cycle description t able for cy7c1 556v18 follows. [3, 11] write cycle descriptions bws 0 k k l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device du ring this portion of a write operation. h ? l?h no data is written into the device du ring this portion of a write operation. the write cycle description t able for cy7c1 545v18 follows. [3, 11] write cycle descriptions bws 0 bws 1 bws 2 bws 3 k k comments lllll?h?during the data portion of a write s equence, all four bytes (d [35:0] ) are written into the device. llll?l?hduring the data portion of a write s equence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl?h?no data is written into the device during this portion of a write operation. hhhh?l?hno data is written into the device during this portion of a write operation. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 12 of 28 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-2001. the tap operates using jedec standard 1.8v io logic levels. disabling the jtag feature it is possible to operate t he sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up inter- nally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the the state diagram for the tap controller follows. [12] on page 14. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is acti ve, depending upon the current state of the tap state machine (see instruction codes on page 17). the output changes on the falling edge of tck. tdo is connected to the least signific ant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serial ly loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 15. upon power up, the inst ruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is conn ected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is l oaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. boundary scan order on page 18 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of t he register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regi ster has a vendor code and other information described in the identification register definitions on page 17. tap instruction set eight different instructions ar e possible with the three-bit instruction register. all comb inations are listed in the instruction codes on page 17. three of thes e instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction regist er is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through t he tdi and tdo pins. to execute the instruction after it is shif ted in, the tap controller must be moved into the update-ir state. idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 13 of 28 between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded in to the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connec ts the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is supplied during the update-ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan regi ster cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently wh en required, that is, the data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loa ded in the inst ruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pi ns. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates t hat the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #108. when this scan cell, called the ?e xtest output bus tri-state?, is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 14 of 28 the state diagram for the tap controller follows. [12] tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 12. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 15 of 28 tap controller block diagram tap electrical characteristics over the operating range [13, 14, 15] parameter description test conditions min max unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and output load current gnd v i v dd ?5 5 a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 108 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 13. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table. 14. overshoot: v ih (ac) < v ddq + 0.35v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 0.3v (pulse width less than t cyc /2). 15. all voltage referenced to ground. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 16 of 28 tap ac switching characteristics over the operating range [16, 17] parameter description min max unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions figure 2 shows the tap timing and test conditions. [17] figure 2. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 gnd 0.9v 50 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 16. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 17. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 17 of 28 identification regi ster definitions instruction field value description cy7c1541v18 cy7c1556v18 cy7c1543v18 cy7c1545v18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010010101000100 11010010101001100 11010010101010100 11010010101100100 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1111indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring c ontents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 18 of 28 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 1j 16p299g575b852j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n329f605c882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 19 of 28 power up sequence in qdr-ii+ sram qdr-ii+ srams must be powered up and initialized in a predefined manner to prevent undefined operations. during power up, when the doff is tied high, the dll gets locked after 2048 cycles of stable clock. power up sequence apply power with doff tied high (all other inputs can be high or low) ? apply v dd before v ddq ? apply v ddq before v ref or at the same time as v ref provide stable power and clock (k, k ) for 2048 cycles to lock the dll. dll constraints dll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the dll functions at frequencies down to 120 mhz. if the input clock is unstable and the dll is enabled, then the dll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. figure 3. power up waveforms k k fix high (tie to v ddq ) v dd /v ddq doff clock start (clock starts after v dd /v ddq is stable) unstable clock > 2048 stable clock start normal operation ~ ~ ~ ~ v dd /v ddq stable (< + 0.1v dc per 50 ns) [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 20 of 28 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65c to +150c ambient temperature with power applied.. ?55c to +125c supply voltage on v dd relative to gnd ... .....?0.5v to +2.9v supply voltage on v ddq relative to gnd.......?0.5v to +v dd dc applied to outputs in high-z ........ ?0.5v to v ddq + 0.3v dc input voltage [14] .............................. ?0.5v to v dd + 0.3v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, m. 3015)... >2001v latch-up current .................................................... >200 ma operating range range ambient temperature (t a ) v dd [18] v ddq [18] commercial 0c to +70c 1.8 0.1v 1.4v to v dd industrial ?40c to +85c electrical characteristics dc electrical characteristics over the operating range [15] parameter description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq io supply voltage 1.4 1.5 v dd v v oh output high voltage note 19 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 20 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [14] v ref + 0.1 v ddq + 0.15 v v il input low voltage [14] ?0.15 v ref ? 0.1 v i x input leakage current gnd v i v ddq ? 2 2 a i oz output leakage current gnd v i v ddq, output disabled ? 2 2 a v ref input reference voltage [21] typical value = 0.75v 0.68 0.75 0.95 v i dd [22] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 375 mhz x8 1300 ma x9 1300 x18 1300 x36 1370 333 mhz x8 1200 ma x9 1200 x18 1200 x36 1230 300 mhz x8 1100 ma x9 1100 x18 1100 x36 1140 notes 18. power up: assumes a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 19. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 <= rq <= 350 . 20. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 <= rq <= 350 . 21. v ref (min) = 0.68v or 0.46v ddq , whichever is larger, v ref (max) = 0.95v or 0.54v ddq , whichever is smaller. 22. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 21 of 28 i sb1 automatic power down current max v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 375 mhz x8 525 ma x9 525 x18 525 x36 410 333 mhz x8 500 ma x9 500 x18 500 x36 395 300 mhz x8 450 ma x9 450 x18 450 x36 385 ac electrical characteristics over the operating range [14] parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? v ddq + 0.24 v v il input low voltage ?0.24 ? v ref ? 0.2 v capacitance tested initially and after any design or process change that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v, v ddq = 1.5v 5 pf c clk clock input capacitance 6 pf c o output capacitance 7pf electrical characteristics (continued) dc electrical characteristics over the operating range [15] parameter description test conditions min typ max unit [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 22 of 28 thermal resistance tested initially and after any design or process change that may affect these parameters. parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 11.82 c/w jc thermal resistance (junction to case) 2.33 c/w figure 4. ac test loads and waveforms 1.25v 0.25v r = 50 5pf including jig and scope all input pulses device r l = 50 z 0 = 50 v ref = 0.75v v ref = 0.75v [23] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 (b) rq = 250 23. unless otherwise noted, test conditions as sume signal transition time of 2v/ns, timing reference levels of 0.75v, vref = 0.7 5v, rq = 250 , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads and waveforms . [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 23 of 28 switching characteristics over the operating range [23, 24] cy parameter consortium parameter description 375 mhz 333 mhz 300 mhz unit min max min max min max t power v dd (typical) to the first access [25] 111ms t cyc t khkh k clock cycle time 2.66 8.40 3.0 8.40 3.3 8.40 ns t kh t khkl input clock (k/k ) high 0.4 ? 0.4 0.4 ? t cyc t kl t klkh input clock (k/k ) low 0.4 ? 0.4 0.4 ? t cyc t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 1.13 ? 1.28 ? 1.40 ? ns setup times t sa t avkh address setup to k cl ock rise 0.4 ? 0.4 ? 0.4 ? ns t sc t ivkh control setup to k clock rise (rps , wps ) 0.4 ? 0.4 ? 0.4 ? ns t scddr t ivkh double data rate control setup to clock (k/k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.28 ? 0.28 ? 0.28 ? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.28 ? 0.28 ? 0.28 ? ns hold times t ha t khax address hold after k clock rise 0.4 ? 0.4 ? 0.4 ? ns t hc t khix control hold after k clock rise (rps , wps ) 0.4 ? 0.4 ? 0.4 ? ns t hcddr t khix double data rate control hold after clock (k/k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.28 ? 0.28 ? 0.28 ? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.28 ? 0.28 ? 0.28 ? ns output times t co t chqv k/k clock rise to data valid ? 0.45 ? 0.45 ? 0.45 ns t doh t chqx data output hold after output k/k clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ns t ccqo t chcqv k/k clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.45 ns t cqoh t chcqx echo clock hold after k/k clock rise ?0.45 ? ?0.45 ? ?0.45 ? ns t cqd t cqhqv echo clock high to data valid 0.2 0.2 0.2 ns t cqdoh t cqhqx echo clock high to data invalid ?0.2 ? ?0.2 ? ?0.2 ? ns t cqh t cqhcql output clock (cq/cq ) high [26] 0.88 ? 1.03 ? 1.15 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise [26] (rising edge to rising edge) 0.88 ? 1.03 ? 1.15 ? ns t chz t chqz clock (k/k ) rise to high-z (active to high-z) [27, 28] ?0.45?0.45?0.45ns t clz t chqx1 clock (k/k ) rise to low-z [27, 28] ?0.45 ? ?0.45 ? ?0.45 ? ns t qvld t cqhqvld echo clock high to qvld valid [29] ?0.20 0.20 ?0.20 0.20 ?0.20 0.20 ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k) 2048 ? 2048 ? 2048 ? cycles t kc reset t kc reset k static to dll reset [30] 30 30 30 ns notes 24. when a part with a maximum frequency above 300mhz is operati ng at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 25. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 26. these parameters are extrapolated from the input timing parameters (t khk h -250ps, where 250ps is the internal jitter. an input jitter of 200ps(t kcvar ) is already included in the t khk h ). these parameters are only guaranteed by design and are not tested in production. 27. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ?ac test loads and waveforms? on page 22. transition is measured 100 mv from steady-state voltage. 28. at any given voltage and temperature t chz is less than t clz and t chz less than t co . 29. t qvld spec is applicable for both risi ng and falling edges of qvld signal. 30. hold to >v ih or cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 24 of 28 switching waveforms read/write/deselect sequence [31, 32, 33] figure 5. waveform for 2.0 cycle read latency t kh t kl t cyc t khkh nop read nop write read write 1 23 4 5 6 7 8 t t t t sa ha sc hc t hd t sc t hc a0 a1 a2 a3 t t sd hd t sd d11 d10 d12 d13 d30 d31 d32 d33 d a wps rps k k dont care undefined cq cq t cqoh ccqo t t cqoh ccqo t t qvld qvld t qvld (read latency = 2.0 cycles) clz t t co t doh t cqdoh cqd t t chz q00 q01 q20 q02 q21 q03 q22 q23 t cqh t cqhcqh q notes 31. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0+1. 32. outputs are disabled (high-z) one clock cycle after a nop. 33. in this example, if address a2 = a1, then data q20 = d10, q21 = d11, q22 = d12, and q23 = d13. write data is forwarded immed iately as read results. this note applies to the whole diagram. [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 25 of 28 ordering information not all of the speed, package and temperature ranges are ava ilable. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 375 cy7c1541v18-375bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1556v18-375bzc cy7c1543v18-375bzc cy7c1545v18-375bzc cy7c1541v18-375bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1556v18-375bzxc cy7c1543v18-375bzxc cy7c1545v18-375bzxc cy7c1541v18-375bzi 51-85195 165-ball fine pitch ba ll grid array (15 x 17 x 1.4 mm) industrial cy7c1556v18-375bzi cy7c1543v18-375bzi cy7c1545v18-375bzi cy7c1541v18-375bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1556v18-375bzxi cy7c1543v18-375bzxi cy7c1545v18-375bzxi 333 cy7c1541v18-333bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1556v18-333bzc cy7c1543v18-333bzc cy7c1545v18-333bzc cy7c1541v18-333bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1556v18-333bzxc cy7c1543v18-333bzxc cy7c1545v18-333bzxc cy7c1541v18-333bzi 51-85195 165-ball fine pitch ba ll grid array (15 x 17 x 1.4 mm) industrial cy7c1556v18-333bzi cy7c1543v18-333bzi cy7c1545v18-333bzi cy7c1541v18-333bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1556v18-333bzxi cy7c1543v18-333bzxi cy7c1545v18-333bzxi [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 26 of 28 300 cy7c1541v18-300bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial cy7c1556v18-300bzc cy7c1543v18-300bzc cy7c1545v18-300bzc cy7c1541v18-300bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1556v18-300bzxc cy7c1543v18-300bzxc cy7c1545v18-300bzxc cy7c1541v18-300bzi 51-85195 165-ball fine pitch ba ll grid array (15 x 17 x 1.4 mm) industrial cy7c1556v18-300bzi CY7C1543V18-300BZI cy7c1545v18-300bzi cy7c1541v18-300bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1556v18-300bzxi cy7c1543v18-300bzxi cy7c1545v18-300bzxi ordering information (continued) not all of the speed, package and temperature ranges are ava ilable. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range [+] feedback [+] feedback
cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 document number: 001-05389 rev. *f page 27 of 28 package diagram figure 6. 165-ball fbga (15 x 17 x 1.4 mm), 51-85195 ! 0).#/2.%2 ? ? ?8 ?-#!" ?-# " ! 8 ? -!8 3%!4).'0,!.% ? # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - . 0 2 0 2 + - . , * ( ' & % $ # " ! # 3/,$%20!$490%./.3/,$%2-!3+$%&).%$.3-$ ./4%3 0!#+!'%7%)'(4g *%$%#2%&%2%.#%-/ $%3)'.# 0!#+!'%#/$%""!$ 51-85195-*a [+] feedback [+] feedback
document number: 001-05389 rev. *f revised march 06, 2008 page 28 of 28 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. cy7c1541v18, cy7c1556v18 cy7c1543v18, cy7c1545v18 ? cypress semiconductor corporation, 2005-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7c1541v18/cy7c1556v18/cy7c1543v18/cy7 c1545v18, 72-mbit qdr?-ii+ sram 4-word burst archi- tecture (2.0 cycle read latency) document number: 001-05389 rev. ecn no. issue date orig. of change description of change ** 403090 see ecn vee new data sheet *a 425252 see ecn vee updated the dll section fixed typos in the dc and ac parameter section updated the switching waveform updated the power up sequence added additional parameters in the ac timing *b 437000 see ecn igs ecn for show on web *c 461934 see ecn nxr moved the selection guide table from page# 3 to page# 1 modified application diagram changed t th and t tl from 40 ns to 20 ns, changed t tmss , t tdis , t cs , t tmsh , t tdih , t ch from 10 ns to 5 ns and changed t tdov from 20 ns to 10 ns in tap ac switching characteristics table modified power up waveform included maximum ratings for supply voltage on v ddq relative to gnd changed the maximum ratings for dc input voltage from v ddq to v dd changed the pin definition of i x from input load current to input leakage current on page#18 *d 497567 see ecn nxr changed the v ddq operating voltage to 1.4v to v dd in the features section, in operating range table and in the dc electrical characteristics table added foot note in page# 1 changed the maximum rating of ambient temperature with power applied from ?10 c to +85 c to ?55 c to +125 c changed v ref (max) spec from 0.85v to 0.95v in the dc electrical characteristics table and in the note below the table updated footnote #21 to specif y overshoot and undershoot spec updated i dd and i sb values updated ja and jc values removed x9 part and its related information updated footnote #25 *e 1351243 see ecn vkn/fsu converted from preliminary to final added x8 and x9 parts changed t cyc max spec to 8.4 ns for all speed bins updated footnote# 23 updated ordering information table *f 2181046 see ecn vkn/aesa added footnote# 22 related to i dd [+] feedback [+] feedback

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